Semiconductor Engineering

Hardware Trojans Target Coherence Systems in Chiplets (Texas A&M / NYU)

A technical paper titled “Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems” was published by researchers at Texas A&M University and NYU. “As industry moves toward ...
Design-Reuse

Using OCP and Coherence Extensions to Support System-Level Cache Coherence

Open Core Protocol (OCP) [1][2] is a common standard for Intellectual Property (IP)core interfaces. OCP facilitates IP core plug-and-play and simplifies reuse by decoupling the cores from the on-chip ...
Semiconductor Engineering

The High But Often Unnecessary Cost Of Coherence

Cache coherency, a common technique for improving performance in chips, is becoming less useful as general-purpose processors are supplemented with, and sometimes supplanted by, highly specialized ...
Design-Reuse

Co-Designed Cache Coherency Architecture for Embedded Multicore Systems

One of the key challenges in chip multi-processing is to provide a programming model that manages cache coherency in a transparent and efficient way. A large number of applications designed for ...
Electronic Design

Formal Methodology Validates Cache-Coherence Protocol

Bugs in RTL code are problematic, but a bug in an architectural specification can be catastrophic. If the bug remains undetected until post-silicon debugging, the design process essentially starts all ...
EDN

Using OCP and extensions to support system-level cache coherence

Open Core Protocol (OCP) is a common standard for Intellectual Property (IP)core interfaces. OCP facilitates IP core plug-and-play and simplifies reuse by decoupling the cores from the on-chip ...