One of the key factors in the design and development of submicron chip designs is the setting of good physical and timing constraints, no matter what type of design methodology you use. Constraints ...

Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.

FPGA devices have grown to ASIC size and complexity, but traditional EDA tools and methodologies have failed to keep pace. Engineers designing high-end FPGAs are beginning to face the types of ...

The move to system-on-chip (SoC) designs is expected to dramatically increase chip sizes from the already complex 10 million to 20 million transistors to more than 100 million transistors in fewer ...

Hierarchical design methodologies that introduce concurrency into the design flow are the answer to burgeoning circuit complexity. Synopsys's Steve Kister discusses various challenges to design ...

Last month, I discussed two key features of the Common Power Format (CPF) that support hierarchical design methodology: boundary port and macro model. These are commands that need to be written to ...

Physical design verification software typically identifies faults in physical layouts by finding design-rule-check (DRC) violations and layout-versus-schematic (LVS) mismatches after layout is ...

Tsukuba, Japan—Hierarchical structures, including organizational structures and computer networks, are mathematically represented as "rooted trees" that connect related nodes with edges. These can be ...