Semiconductor Engineering

Universal Verification Methodology Running Out Of Steam

For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, ...
EDN

Formal-based methodology cuts digital design IP verification time

When we talk about the signoff of digital IP, we are referring to the full verification of a block. Every feature listed in a device’s datasheet requires verification. Furthermore, every register ...
EDN

A SystemC-based UVM verification infrastructure

My company, TVS, recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless ...
Semiconductor Engineering

Inside UVM

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t ...
Semiconductor Engineering

Updated UVM Cookbook Supports IEEE 1800.2 Standard And Emulation

I’m happy to announce that we at Mentor have just released a fully-updated version of our popular UVM Cookbook, which is available online here. Cookbook Overview Diagram The Universal Verification ...
Semiconductor Engineering

Extending UVM To Analog

Analog/mixed-signal content in SoCs needs to be modeled in a similar way as the digital content but does UVM make sense for pure analog? Perhaps not. As SoC complexity has grown, so too has the need ...
Yahoo

EVE's ZeBu SystemVerilog Approach Used by Fujitsu Kyusyu Network Technologies to Implement UVM Co-Emulation

SAN JOSE, CA--(Marketwire -09/04/12)- EVE, the leader in hardware/software co-verification, today announced that its ZeBu hardware-assisted verification platform and SystemVerilog methodology have ...
EDN

UVM—the star of DVCon 2011

What's all the buzz on UVM? The quite successful 2011 Design and Verification Conference was held last week. The most prominent topic at the conference was the Universal Verification Methodology (UVM) ...
Business Insider

Accellera Board Approves Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 Standard for Release

ELK GROVE, Calif., Feb. 04, 2025 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design ...
Semiconductor Engineering

Universal Verification Methodology Coverage For Bluespec RISC-V Cores

Attempting to achieve complete RISC-V verification requires multiple methodologies, one of which is coverage driven simulation based on UVM constrained random methods and complaint with the Universal ...