IEEE

Automated Verilog Assertion Generation Using Fine-Tuned LLMs with Subtask-Specific Iterative Prompting

Abstract: Formal Property Verification (FPV), using System Verilog Assertions (SVA), is crucial for ensuring the completeness of design with respect to the specification. However, writing SVA is a ...
IEEE

AVERT: An Automatic Verilog Testbench Generation Tool for Grammatical Evolution

Abstract: With the ever-growing complexity of digital circuits, the appeal of using Machine Learning in digital circuit design has grown significantly. Over the last 25 years, Evolutionary Algorithms ...
GitHub

eBPF Developer Tutorial: Learning eBPF Step by Step with Examples

This is a development tutorial for eBPF based on CO-RE (Compile Once, Run Everywhere). It provides practical eBPF development practices from beginner to advanced, including basic concepts, code ...
GitHub

ECE 4750 Section 2: RTL Design with Verilog

This repository contains the code and documentation for ECE 4750 Section 2 on the RTL design with Verilog. You can find the actual section document in the repo here: ...